Scientists crack key barrier in AI memory technology

Researchers at Belgian semiconductor institute imec have announced two breakthroughs in a type of memory technology that many in the chip industry believe could solve one of AI's most pressing hardware problems: the looming collapse of conventional memory.

The findings, presented Tuesday at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits in Kyoto, target what engineers call ferroelectric memory — a class of chip storage that can hold data without continuous power, switch states at low voltages, and potentially pack far more information into a smaller space than today's standard memory chips.

AI workloads are consuming memory at a pace that conventional technology was never designed to handle. The dominant chip memory standard, DRAM, is approaching the limits of how small and efficient it can be made — and the cost and energy demands of scaling it further are becoming untenable for data centers running AI at scale.

On the way to faster memories

imec's first result addresses the reliability of ferroelectric capacitors, a core memory building block. The team demonstrated that these devices can operate at roughly 1.3 volts — low enough to meaningfully cut power consumption — while enduring more than ten trillion data cycles without failure. That level of durability is a prerequisite for any memory technology hoping to compete in AI infrastructure, where chips run continuously under heavy load.

The second result is more structurally novel. imec built the world's first working vertical stack of five ferroelectric memory transistors, layered directly on top of one another in a single column. The technique — already familiar from flash storage in solid-state drives — has never been successfully demonstrated for this type of device. Stacking vertically multiplies storage density without requiring ever-finer chip manufacturing, a key advantage as traditional scaling hits its limits.

Sustaining the growth of AI

The team also solved a longstanding flaw in this class of transistor: difficulty erasing stored data. By adding a second gate to the device architecture, researchers significantly improved erase efficiency — a fix that moves the technology closer to practical use.

Attilio Belmonte, a program director at imec, said the results demonstrate how advances in materials science and chip integration can work in tandem. "This work shows how imec's multidisciplinary expertise enables us to tackle some of the most pressing challenges in memory technology," he said. Colleague Maarten Rosmeulen added that the institute is "exploring multiple paths toward the memory solutions that will be required to sustain the rapid growth of AI."

Neither technology is ready for commercial production. The research center says further work is needed on manufacturing consistency and long-term reliability before either approach could appear in real AI hardware. The institute plans to begin system-level testing next, integrating the devices into full-chip architectures to evaluate their performance under real-world conditions.